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4 General Circuit Description
This single-chip radio transceiver provides a complete radio transceiver interface
between an antenna and a microcontroller. It comprises the analog radio, digital
modulation and demodulation including time and frequency synchronization and data
buffering. The number of external components is minimized such that only the antenna,
the crystal and decoupling capacitors are required. The bidirectional differential antenna
pins (RFP, RFN) are used for transmission and reception, thus no external antenna
switch is needed.
The Atmel AT86RF232 block diagram is shown in Figure 4-1 .
Figure 4-1. AT86RF232 Block Diagram.
PA and Power Control
XOSC
AVREG
Configuration Registers
PA
PLL
TX Data
TX BBP
DVREG
SPI
/SEL
MISO
RFP
RFN
FTN, BATMON
Frame
Buffer
(Slave)
MOSI
SCLK
LNA
PPF
BPF
Limiter
ADC
RX BBP
AES
IRQ
CLKM
DIG2
DIG1/2
AD
Analog Domain
Antenna Diversity
AGC
RSSI
Control Logic
Digital Domain
/RST
SLP_TR
The received RF signal at pin 5 (RFN) and pin 6 (RFP) is differentially fed through the
low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the
integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the
succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The
ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping
and 32-length block coding (spreading) according to [1] and [2]. The modulation signal
is generated in the digital transmitter (TX BBP) and applied to the fractional-N
frequency synthesis (PLL), to ensure the coherent phase modulation required for
demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power
amplifier (PA).
8
AT86RF232
8321A – MCU Wireless – 10/11
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